Custom computing architectures that employ FPGAs have been shown to provide significant improvements in computational performance and energy efficiency over traditional programmable processors. These benefits are possible due to the ability to customize a hardware circuit to a single computation and to replicate this computation many times. These computational benefits, however, are limited to those hardware circuit designers who have the skills to design FPGA circuits. This project is investigating techniques and tools for improving the productivity of FPGA design. A variety of tools have been created at BYU to facilitate FPGA design productivity including JHDL, RapidSmith, TINCR, and EDIFTools. RapidSmith is a research-based, open source FPGA CAD tool written in Java for modern Xilinx FPGAs. Based on XDL, its objective is to serve as a rapid prototyping platform for research ideas and algorithms relating to low level FPGA CAD tools.